In semiconductor integrated circuit (IC) fabrication processes, the resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. To continue to use fabrication equipment purchased for larger technology nodes, multi-exposure methods have been developed.
Multiple exposure or multi-patterning technology (MPT) involves forming patterns on a single layer over a substrate using two or more different masks in succession. As long as the patterns within each individual mask comply with the relevant minimum separation distances for the technology node, the combination of patterns formed using the plural masks may include smaller spacings than the minimum separation distance. MPT allows line segments, and in some cases, vertices (angles) to be formed of a vertical segment and a horizontal segment on the same mask. Thus, MPT provides flexibility and generally allows for significant reduction in overall IC layout.
MPT is a layout splitting method analogous to an M-coloring problem for layout splitting in graph theory, where M is the number of masks used to expose a single layer (and the number of exposures). For example, if two masks are to be used (double patterning technology, DPT), it is customary to refer to the patterns as being assigned one of two “color types”, where the color corresponds to a photomask assignment. As used herein, DPT is an example of MPT, so that generic references to MPT include DPT as one non-limiting example.
If every possible combination of mask assignments violates the minimum spacing rule in either or both of the masks used for DPT, then the layout has a “native conflict”. DPT alone does not avoid the native conflict.